1. Field of the Invention
The present invention relates to a method and a device for arbitrating access to a resource shared by several elements.
2. Description of the Related Art
FIG. 1 schematically represents an example of a device for arbitrating access to a shared resource. A group of master circuits M0, M1, . . . Mi, . . . Mn are linked to a shared resource through a multiplexer circuit BMUX. The shared resource here comprises a bus BSH and at least one peripheral circuit PPH linked to this bus, for example a data and/or instruction memory forming a slave circuit. The group of master circuits comprises for example microprocessors, a DSP processor, co-processors, a DMA circuit (direct memory access circuit), an embedded video camera . . . . Such a combination of circuits sharing a common resource is frequent in integrated circuits for new generation mobile telephones.
Accesses to the memory PPH are arbitrated by an arbitrating device ACT1 that receives access requests R0, R1, . . . Ri, . . . Rn supplied by each of the master circuits and which supplies a selection signal SEL to a control input of the circuit BMUX, by applying a determined arbitration rule. The requests Ri and the cycles for accessing the shared resource are clocked by a clock signal common to the master circuits, which enables the accesses to the shared resource to be synchronized.
To date, the known arbitration methods are not very satisfactory or adapted to the increasingly complex combinations of master circuits having different roles and different needs in terms of access to the shared resource, certain circuits needing to access the resource regularly but in a way that only represents a small part of the access possibilities offered by the resource, other circuits having irregular access needs that can sometimes be significant at determined periods, and insignificant outside these periods.
Thus, high data rate master circuits can be distinguished that are relatively insensitive to the latency time (waiting time between the accesses to the shared memory). These are for example microprocessors, processors or DSPs (digital signal processor) that need to access the shared memory often but can wait for the memory to be available to perform the operations requiring such an access.
Master circuits can also be distinguished which have a low data rate but are sensitive to the latency time, i.e., they have difficulty delaying the access to the shared memory. These are particularly circuits having a small buffer memory that must regularly exchange data with the shared memory, such as DMA circuits (memory access management circuits), particularly when these circuits supply data to a communication peripheral (USB port, etc.). A video camera must also transfer several images per second into the shared memory, when it is used, then it practically no longer requires access to the memory between two transfers of images. Such a video camera must therefore be able to access the shared memory regularly, so as not to lose data, since its buffer memories can only store a fraction of image (some tens or hundreds of image dots).
High data rate master circuits can also be distinguished that require a minimal and almost immediate access to the shared memory. These are for example microprocessors or DSPs in interrupt mode, that must transfer or read data (data and/or instructions) in the memory at any instant, according to external events causing interrupts, without obeying a determined law of recurrence. Such circuits therefore have a great need to be able to access the peripheral memory “instantly”, i.e., waiting as little as possible.
Finally, master circuits can be distinguished that have a low and consistent data rate but which operate temporarily outside their usual specifications. Thus, a DMA circuit may sometimes need to access the memory almost instantly (short latency time), for example upon the transfer of a considerable amount of data, and sometimes have a considerable need to access the memory for high data rate transfers while being relatively insensitive to the latency time. A video camera, outside its cyclical data rate corresponding to a transfer of images, may sometimes require a high data rate.
When all is said and done, a same master circuit can come under several of the above categories, and have different access needs at different instants.
Now, the classical arbitration methods such as fixed and hierarchized priority arbitration (priority by ascending or descending rank) or rotating priority arbitration (“Round Robin” method) do not optimize the sharing of a resource when there is a plurality of master circuits of the aforementioned type, each having different access needs likely to vary in time.